1. Field of the Invention
This invention is generally related to a method for interconnecting integrated circuits with high volumetric efficiency and, more particularly, to a method of selectively interconnecting the edge contact areas of a plurality of tightly stacked substrates having integrated circuit patterns thereon with edge metallization contact areas.
2. Description of the Prior Art
Interconnecting high performance circuits, such as very large scale integrated circuit (VLSI) chips, presents the circuit designer with several problems. VLSI chips often have one hundred or more pins where the pins have a pitch of less than ten mils. That is to say, the sum of the line width plus the distance between two lines is less than ten thousandths of an inch. The VLSI chips typically must be joined to a circuit board which has a pitch of twenty five to fifty mils. In order to connect the VLSI chip to the circuit board, a "fan out" region of interconnecting lines must be provided. The fan out region occupies valuable space on the circuit board and the long lead lengths contribute high inductance. Thus, the fan out design limits the high speed capability of the circuit. In multichip substrates, which are comprised of numerous chips mounted on the same substrate, interconnections among chips on the substrate allow high speed performance, but substantial performance loss occurs in going from the substrate to the printed circuit board. Not only is soldering several hundred pins on twenty five mil centers a very difficult task, but in addition, thermal mismatch complications and hermeticity problems affect the size of substrate which can be created. According to Rent's rule, the number of pins required increases in accordance with the square root of the number of gates enclosed by the circuitry. Since each pin must be hermetically sealed, the advantage of multichip substrates is severely limited by the unavailability of hermetic packages which can seal more than about three hundred pins.